1. Technical Field
The present disclosure relates generally to a semiconductor device and more particularly to a unit array of a memory device, a memory device, and a memory system including the unit array.
2. Description of the Related Art
In case one bit data is read from a memory cell array, the one bit data may be ‘0’ or ‘1’. To determine whether the one bit data that is read from the memory cell array is ‘0’, the first reference bit corresponding to data ‘0’ may be used. In addition, to determine whether the one bit data that is read from the memory cell array is ‘1’, the second reference bit corresponding to data ‘1’ may be used. The one bit data, the first reference bit and the second reference bit may be stored in the memory cell array. The read speeds of the one bit data, the first reference bit and the second reference bit from the memory cell array may be different.